Highly robust 0.25-/spl mu/m single-poly-gate CMOS with inter-well deep trenches

An advanced buried channel PMOS was precisely compared with a surface channel counterpart, and it was shown to maintain advantages for the 0.25-/spl mu/m generation. 0.25-/spl mu/m single-poly-gate CMOS combined with deep-trench inter-well isolation showed high robustness to latchup, soft errors and ESD, and attained a 1.8/spl times/ speed performance improvement relative to 0.5-/spl mu/m CMOS in a typical logic gate and a 48/spl times/48-bit multiplier.