The RD27 muon trigger co-incidence array demonstrator ASIC

One aim of the RD27 project is to perform design and R&D work leading to a first level muon trigger for an experiment at the Large Hadron Collider (LHC) at CERN. This paper describes the design, implementation and testing of an ASIC for a trigger demonstrator system. The trigger system is implemented using a set of seven chambers. The low momentum trigger requires hits in three out-of the four inner chambers. The high momentum trigger requires a low momentum trigger and hits in two of three outer chambers. This scheme allows for chamber inefficiencies for real muons and reduces the trigger rate from neutron and photon-induced background in the detectors. The core of the ASIC is an eight by twenty-four input 'double' co-incidence array allowing two momentum cuts to be applied. The ASIC has multiple inputs per axis and includes the multiplicity logic. The design of the ASIC is flexible enough to demonstrate fully combinatorial operation, fully pipelined operation, or any combination of the two. The ASIC has been fabricated using a 34k gate, 0.5 /spl mu/m CMOS gate array from Fujitsu. Testing confirms it can be pipelined at above 100 MHz or fully combinatorial with a measured maximum propagation delay of 7.4 ns, varying by up to 2 ns depending on input pattern.