Partitioning strategy for LUT-based applications using genetic algorithms

In system-level design using hardware-software co-design approaches, applications involved in embedded systems are usually represented as data flow diagrams (DFD) where nodes may either be implemented in software or in hardware, subject to cost-performance constraints. In our research paper, we present how genetic algorithms can be used in order to perform hardware-software partitioning of applications which graph nodes can be implemented in hardware as look-up tables (LUT). These applications are characterized by fixed communication delays and accurate cost predictions which help to reach cost-effective implementations. Results of the proposed approach applied on a 3D range measurement application are presented.