Fault Tolerant and Low Energy Write-Back Heterogeneous Set Associative Cache for DSM Technologies

This paper presents a fault tolerant and energy efficient write-back set-associative cache, which has a heterogeneous structure. The cache architecture is based on partitioning the ways of each set into two different parts. In each set, one cache way uses SEC-DED code and maintains dirty blocks while the other ways employ parity bit and keep clean blocks. To evaluate the set-associative cache, SIMPLESCALAR tool and CACTI analytical model are used. The experimental results show that as the feature size decreases and the associativity increases, the energy saving of the proposed cache increases. The experimental results express that for an 8-way set-associative cache in 32 nm, about 7% area and 2%-17% energy consumption are saved. These figures are achieved by keeping the reliability in the same level of the conventional SEC-DED protected cache.