Future technology challenge for giga bit DRAM generation

Cost/performance DRAM developments in the industry have followed a set of remarkably consistent trends in cell area, chip area and performance for the last seven generation from 64K to 256 Mb and very likely through the eighth of 1Gb DRAM. New concepts on device and circuit design as well as technology innovations have been the key to allowing these trends to be met. The giga bit generation will very likely require a new breakpoint if the trends are to be continued. A few major areas of technology innovations have been key to the requirements, such as the lithography shrink ability (l.4/spl times/ each generation), levels of metallization and fundamental limitation of device scaling to meet performance goal (1.25/spl times/ chip level), high dielectric materials due to cell area reduction to meet cell capacitance, etc. The system designers will require higher performance. We must decide whether we tackle performance by a technological or by an architectural solution or both. This paper presents the highlights of the technology and concepts for future DRAMs with a focus on its key technology issues.