A Scalable 3.6-to-5.2mW 5-to-10Gb/s 4-tap DFE in 32nm CMOS

This paper presents a power-scalable 5-to-10Gb/s 4-tap DFE that provides further power savings by using three circuit techniques: 1:2 demultiplexed current- integrating summer, sense-amplifier (SA) latched-decision feedback, and fully differential current-recycled DACs (l-DACs).