A Stream-Mode Based HW/SW Co-Emulation System for SOC Test and Verification

With the growing System-on-a-chip (SOC) design complexity, SOC test and verification has become a major bottleneck. In this context, efficient and reliable test and verification system are requested for SOC design before a SOC is committed to production. HW/SW co-emulation system combing software simulation with hardware acceleration is one of dominant systems, where interrupt-based communication mechanism is usually utilized. However, communication overhead will be resulted from data exchange between hardware side and software side at every cycle. A stream-mode based HW/SW co-emulation system is proposed and presented in the paper. In the proposed system, software side sends stimulus data and receives response data continuously while hardware side is testing System-under-Test (SUT) and generating response data. Communication traffic is reduced due to only time spent on software executions with hardware executions, sending and receiving data implemented in parallel. Experiment result demonstrates that stream-based communication mechanism can improve communication throughput by more than 10 folds compared to interrupt-based communication mechanism.