CMOS ESD protection structures-characteristics and performance comparison

The performance of ESD protection structures is highly dependent on process parameters, circuit and layout effects, and the structure's area and geometry. The goal of the work reported here was to produce the best ESD protection structure in a standard 0.8 /spl mu/m N-well CMOS LDD non-silicided process, under the constraint of a given area that is dictated by the pad's pitch (132 /spl mu/m/spl times/65 /spl mu/m), and without adding steps to the process. Basic building blocks of CMOS ESD protection structures are reviewed. Layout and circuit effects are discussed. Several ESD protection structures were tested and their performance was compared. DC characteristics and ESD zapping results are reported. 10 kV HBM ESD protection structures are disclosed.