Static and noise characterization of deep submicron CMOS devices

Today, 0.35 /spl mu/m CMOS technologies have been brought up to integrated circuit mass production. The trend for the next two years is to implement the forthcoming 0.25 /spl mu/m CMOS and the 0.18 /spl mu/m CMOS technologies. Thus deep submicron CMOS is a reality from the standpoint of the CMOS IC market as a very well mastered device. Nevertheless, this device still is an object of interest for applied physicists and engineers since new and interesting phenomena show up (e.g. random telegraph signal or RTS), that are believed to be at the source of enhanced excess noises commonly observed in them. Due to the importance played by noise in analogue circuits applications, specific noise studies have been made of these devices. The present paper provides a summary of the actual knowledge on this topic.