Latent interface-trap generation during thermal annealing of /spl gamma/-ray irradiated power VDMOSFETs

The behaviour of the threshold voltage in commercial n-channel power VDMOSFETs during biased thermal annealing, following /spl gamma/-ray radiation exposure, is investigated. It is found that 'rebound' effect, observed in transistors irradiated and annealed with positive gate bias, is mainly due to the 'latent' interface-trap generation. Possible mechanism for latent interface-trap buildup is proposed.