Synthesizing testability features into a design with the Synopsys Test Compiler

In this paper, we present a methodology for synthesizing testability features in a design described using Hardware Description Language (HDL) and the Synopsys Test Compiler tool. Because an HDL described design of an IC device can be automatically transformed into a gate-level implementation for a given technology with Synopsys Synthesis Tools, adding internal scan test circuitry or boundary scan test circuitry can be easily achieved with the Synopsys Test Compiler. We will discuss scan styles, test methodologies, test pattern generation, as well as the application and format of test patterns.