A generic analytical model of switching characteristics for efficiency-oriented design and optimization of CMOS integrated buck converters

Power management and supply generation is an important issue in SOCs (system on chips). Design of on-chip CMOS buck converters for maximum efficiency needs models which can predict different kinds of losses in the converters. In this paper a generic analytical model for switching times and accordingly I-V overlap losses for on-chip CMOS synchronous buck converters is presented. The model features the derivation of the delay on the basis of change in the stored charge during switching of internal capacitances. Therefore the proposed model needs only a few process parameters to estimate the delays and accordingly I-V overlap losses. Another feature of the presented model is that it's independent of the switch driver and is applicable to a wide range of input voltage and load conditions. The proposed model is implemented in MATLAB and verified against detailed CADENCE Spectre simulations for integrated buck converter design and optimization. Estimations from the model match detailed simulation results for the input voltage range of 2.8 V to 5 V and load current range of 65 mA to 200 mA, which are also presented in this paper. We demonstrate application of the proposed model for elaborative and efficient design space exploration for efficiency-oriented design of buck converters.