A variable-precision systolic architecture for ANN computation

When Artificial Neural Networks (ANNs) are implemented in VLSI with fixed precision arithmetic, the accumulation of numerical errors may lead to results which are completely inaccurate. To avoid this, we propose a variable-precision arithmetic in which the precision of the computation is specified by the user at each layer in the network. This paper presents a top-down approach for designing an efficient bit-level systolic architecture for variable precision neural computation.