Modeling of integrated circuit yield loss mechanisms

A yield model suited for application in a yield control system and based on in-line inspections of control wafers containing the corresponding test structures has been proposed. It is shown that the proposed yield model and yield control system can be used for modeling yield loss mechanisms and predicting efficient investments which are required in order to ensure a competitive yield of integrated circuits. An approach for the extraction of chip critical areas associated with the corresponding yield loss mechanism has been described.