Parameterized hardware design on reconfigurable computers: An image registration case study

Reconfigurable computers (RCs) with hardware (FPGA) co-processors can achieve significant performance improvement compared to traditional computers for certain categories of applications. The potential amount of speedup an RC can deliver depends on the intrinsic parallelism of the target application as well as the characteristics of the target platform. In this paper, we use image registration implementation as a case study to show how a hardware implementation is parameterized by co-processor architecture, particularly the local memory layout. Image registration is a fundamental task in image processing used to match two or more pictures taken at different times, from different sensors, or from different viewpoints. One of several basic transformations in image registration is rigid-body transformation, which is composed of a combination of a rotation thetas, a translation (t
_x
,t
_y
), and a scale change (s). In this work, rigid-body transformation is applied on the test image to register it with the reference image; and correlation coefficient is used as the similarity metric between the two images. Two different algorithms, exhaustive search algorithm and discrete wavelet transform (DWT)-based search algorithm, are implemented on hardware (i.e., FPGA device on Cray XD1 reconfigurable computer). The hardware implementation of exhaustive search algorithm is 10times faster than the software implementation. The performance improvement of DWT-based search algorithm in hardware is roughly 2 folds compared to the corresponding software implementation.