Low-frequency measurements and modeling of MLC capacitors

A model based on electron trapping at interface states is described which predicts a t/sup -n/ dependence for leakage current, where n>or=1. The interface can be metal-ceramic or grain boundary. The model has two requirements: that the trap filling rate be proportional to the density of empty traps, and that the interface be inhomogeneous (patchy), such that the active area (i.e. the area with unfilled traps) decreases with time. Near room temperature (>or approximately=75 degrees C), the model predicts that n should be near unity, capacitance should decrease logarithmically with time and be dispersion free, and conductance should increase linearly with frequency. As conduction current becomes significant (at temperatures above about 100 degrees C), the model predicts that n should approach zero, conductance dispersion should decrease to zero, and low-frequency capacitance should vary inversely with frequency. Decay parameter n, therefore, should vary linearly with time and voltage and exponentially with temperature. All of these predictions are confirmed to a substantial degree by measurements made on commercial X7R, Z5U, and Y5V MLC (multilayer ceramic) capacitors, with the agreement for Y5V being very good. Such low-frequency dispersion is similar to that seen for a GaAs Schottky diode with a damaged metal-semiconductor interface.<
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