Single-Phase Multilevel PWM Inverter Topologies Using Coupled Inductors

The number of voltage levels available in pulsewidth modulation (PWM) voltage source inverters can be increased by using a split-wound coupled inductor within each inverter leg and interleaved PWM switching of the upper and lower switches. The magnetizing inductance of the symmetrical split-wound inductor filters the high-frequency PWM voltage differences between the upper and lower switches. The same inductor presents a three-level PWM voltage at the inverter output terminals, with the winding leakage inductance being located in series with the low-frequency output current. Deadtime PWM signal delays can be reduced as DC-rail short circuits are not possible: as a result, the quality and voltage range of the PWM output is improved. Since the inductor windings are technically exposed to high-frequency PWM AC voltages with no DC components, device voltage drops help to reduce the buildup of winding DC currents. Theoretical analysis and a sample design case are presented to illustrate how to design suitable inductors for the various topologies. Simulation and experimental results are used to illustrate the operation of the proposed inverter structures.