A hierarchical register optimization algorithm for behavioral synthesis

In this work, we address the problem of register optimization that arises during high-level synthesis from hierarchical behavioral specifications containing a hierarchy of modules such as procedures, functions etc. Register optimization (or register sharing) is the process of grouping carriers in the specification such that each group can be safely assigned to a hardware register. Global register optimization by in-line expansion involves flattening the module hierarchy and using a heuristic register optimization procedure on the flattened description. Although in-line expansion leads to near-optimal number of registers, it is time consuming due to the large number of carrier compatibility relationships that must be considered. We present an efficient register optimization algorithm which achieves nearly the same effect of in-line expansion without actually in-line expanding at the specification level. It differs from other techniques as it employs a hierarchical optimization phase which exploits the properties of the module call graph and the information gathered during local carrier life-cycle analysis of each module. Experimental results on a number of examples show that the proposed algorithm produces nearly the same number of registers as in-line expansion based global optimization and is faster by a factor ranging from 1.5 to 18.3.