High performance bi-directional FIFO for bus interface applications

Specialty Memory Devices, such as FIFOs, derive their high performance from their architecture as well as their underlying technology. The need for higher speed in FIFOs has resulted in the introduction of faster and faster devices, with access times as low as 10 ns, such as the QS7204-10. Nevertheless, traditional FIFO interfaces, even at the 10 ns access time level, fall short of meeting today's leading edge CPU performance requirements. Additionally, data width requirements use large amounts of board space either because of large pin counts or multiple packages. Moreover, the traditional FIFOs have had limited drive capability that have precluded them from use as direct bus interface devices. Clocked interfaces allow better utilization of the memory bandwidth and can provide data rates in excess of 66 MHz in real world system environments. Buffer-like output drive capability allows for direct bus interface, eliminating the need for additional components. These features, combined in the VSOP package, enable high performance, high density system designs. This paper focuses on three aspects of FIFOs: speed, drive capability, and packaging technology and shows how these enhancements can boost system performance and board efficiency.