Synthesis for advanced ASIC design

This paper describes a new synthesis capability required for the design of advanced ASICs. Called placement-based synthesis (PBS), it specifically addresses the challenges of 0.5 /spl mu/m design. It allows placement data to be read by logic design tools in order to accurately assess interconnect delays (which account for up to 80% of the overall delay through a path in devices of this size). It then directly and incrementally adjusts the placement in order to correct timing problems and meet performance objectives.