Synaptic weight generation in VLSI stochastic neural networks

Fully parallel stochastic neural network implementations can be realized nowadays. However, in these implementations most of the silicon area is consumed in the stochastic pulse sequence generation circuits. In order to improve their efficiency in terms of consumed silicon area, new techniques must be developed. This is specially important in applications where a large number of synaptic weights are needed. In this paper we present a new approach that can significantly increase the efficiency of the technique that has been used up to now.