Hardware implementation of a VDPCM using parallel processing architecture

A parallel processing architecture is described to implement the VDPCM encoder/decoder hardware for real-time image coding applications. The architecture consists of processing elements in modular form, and each module is designed around AT&T's DSP32 chip. The system is flexible and expandable. The hardware was used to encode images at a rate of 0.5 bit pixel, and results are given. The hardware results are in agreement with the computer simulations.<
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