A 128k 6.5 ns access/5 ns cycle CMOS ECL static RAM

The authors describe an experimental 128k CMOS ECL-(emitter-coupled-logic)-compatible static RAM which has pipelined architecture and circuit techniques providing 6.5-ns first access and 5-ns cycle operation for fully random read/write. Using an all-CMOS technology, this cycle, combined with the 32-bit data I/O (input/output) capability, offers data bandwidth as high as 6.46 Gb/s. The technology is 1.2- mu m n-well CMOS with 14-nm gate oxide, 0.5- mu m effective channel length, and three levels of metal. The chip features a pin-selectable 32- or 8-bit-wide data I/O interface, transition-rate-controlled data outputs, low standby power, and well-controlled di/dt. To achieve high-speed operation and maximum power distribution efficiency, the chip is partitioned into 32 4k subarrays, organized into four quadrants. Operation using a pipelined chain of self-resetting circuit macros, initiated by a single clock, is shown. Measured waveforms are presented which illustrate the 6.5-ns access time and the 5-ns cycle time for a read '1' followed by a read '0' operation on the same data pin.<
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