A 64 b RISC microprocessor for a parallel computer system

A description is given of a microprocessor that is designed as a processing element (PE) of a parallel computer system, executing a 64-b floating-point ADD/SUB/MULT in 50 ns and a DIV in 350 ns because of its pipelined structure and dedicated floating-point blocks. The processor employs RISC (reduced-instruction-set-computer) architecture and executes most of its 47 instructions in one 50-ns cycle. The chip is fabricated in 1.2- mu m n-well CMOS technology and contains 440 K transistors in a 14.4*13.5-mm/sup 2/ die. The processor provides high-speed double-precision floating-point operation, high reliability in data handling, communication capability between PEs and the host controller device, and hardware support for efficient code generation by the compiler. The maximum performance of the processor is 20 MFLOPS (million floating-point operations per second) or 20 MIPS (million instructions per second). Typical performance is 4 MFLOPS, measured during execution of Gaussian elimination operation. The major characteristics and performance of the processor are summarized.<
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