A 50 MIPS (peak) 32/64 b microprocessor

An RISC (reduced-instruction-set-computer) microprocessor is described that, subject to data dependencies, can issue one 32-b instruction every 20-ns cycle to achieve peak performance of 50 MIPS (million instructions per second) for worst-case process and operating conditions. The chip includes a 64-b by 32-b general-purpose register file, a 22-b by 32-b privileged-register file, a 1 kB eight-way-associative virtual instruction cache, a 2-kB direct-mapped write-through physical data cache, an 8-entry fully associative instruction address translation buffer, a 32-entry fully associative data address translation buffer, a 10-entry by 64-b output data FIFO, 3-entry by 64-b instruction input FIFO, a 2-entry by 64-b data input FIFO, hardware support for multiprocessing, and a heavily pipelined integer execution unit. Although the execution unit has a 32-b datapath, the data cache, external interface, and register file are organized by 64 b to maximize data transfer rates and to allow single-cache issue of all double-precision instructions. The chip is fabricated in a 1.5- mu m drawn n-well double-metal CMOS process. It contains 294353 transistors, of which 135680 are in the cache arrays, measures 14.5 mm*9.5 mm, and is mounted in a 224-pin surface-mount leaded chip carrier. Power dissipation is 9 W at a 20 ns cycle time.<
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