A design verification kit for passive RFID system on a Chip

The spread of RFID application need IC-based solution to reduce the size and cost of reader. The IC result and architecture of design verification kit for UHF band passive RFID system on a chip is presented in this paper. The kit includes process core, RFID digital baseband, 10bit-differention DAC/ADC, RF based on direct-conversion architecture, user interface block and software. RFID protocol meets the EPC Class-1 Generation 2 and ISO-18000-6C standards. The Chip made by verifying reader protocol using this kit have similar architecture and can cover all passive RFID frequency range from 860MHz to 960MHz and provide low power consumption as 78mA from 1.8V when output power is +5dBm. The package is 8mm × 8mm CABGA from 5mm × 5mm die area.