A design for passive RFID system on a chip

The spread of RFID application need IC-based solution to reduce the size and cost of reader. The design result and architecture of UHF band passive RFID reader system on a chip is presented in this paper. The chip includes processor core, Flash memory, RFID digital baseband, DAC/ADC, RF based on direct-conversion architecture, user interface block. RFID protocol meets the EPC Class-1 Generation 2 and ISO-18000-6 C standards. The chip can cover all passive RFID frequency range from 860 MHz to 960 MHz and provide low power consumption as 78 mA from 1.8 V when output power is +5 dBm. The package is 8 mm x 8 mm CABGA made with 4 mm x 4 mm die area.