32nm gate-first high-k/metal-gate technology for high performance low power applications

A 32nm gate-first high-k/metal-gate technology is demonstrated with the strongest performance reported to date to the best of our knowledge. Drive currents of 1340/940 μA/μm (n/p) are achieved at I
off
=100 nA/μm, V
dd
=1V, 30nm physical gate length and 130nm gate pitch. This technology also provides a high-Vt solution for high-performance low-power applications with its high drive currents of 1020/700 μA/μm (n/p) at total I
off
∼1 nA/μm @ V
dd
= 1V. Low sub-threshold leakage was achieved while successfully containing I
boff
and I
goff
well below 1nA/um. Ultra high density 0.15 um
²
SRAM cell is fabricated by high NA 193nm immersion lithography. Functional 2Mb SRAM test-chip in 32nm design rule has been demonstrated with a controllable manufacturing window.