Effects of drain bias on threshold voltage fluctuation and its impact on circuit characteristics

Enhancement mechanism of Vth fluctuation in saturation region is analyzed through addressable transistor array measurement and 3D Monte-Carlo TCAD simulation. It was confirmed that random dopant fluctuation (RDF) in heavily doped halo devices enhances source-drain asymmetry, resulting in non-Gaussian distributions of DIBL and saturation Vth (Vth_sat). The measured DIBL behavior was accurately modeled and implemented in statistical circuit simulation, to evaluate the impact on SRAM stability. Optimization of halo for mitigating RDF is important for achieving aggressively scaled SRAM cells.