Copper line topology impact on the reliability of low-k SIOCH for the 45nm technology node and beyond

The introduction of SiOCH low-k dielectrics in copper interconnects associated to the reduction of the critical dimensions in sub 45 nm node technologies is a challenge for reliability engineers. Circuit wear-out linked to low-k dielectric breakdown is now becoming a major concern. With the reduction of the line to line spacing, the control of the line shape and the spacing uniformity within wafer are becoming first order parameters governing the low-k dielectric reliability. Improving the low-k reliability requires then to discriminate each topological effect and quantify its impact on the lifetime at product level. This paper demonstrates that the copper line shape induces a preferential breakdown of the dielectric close to the SiOCH/SiCN capping even at the product nominal voltage. The impact of the line edge roughness (LER) is studied with the introduction of a simple analytical model. Moreover, the impact of the roughness on the product lifetime has been quantified. It's demonstrated that the line to line spacing variation is less critical at the nominal voltage than at high voltage stress. Finally, the impact of the mean spacing variation die to die on the Weibull slope depending of the stress voltage is studied.