2-D DCT using on-line arithmetic

Presents a VLSI architecture for the evaluation of the (8/spl times/8)-point 2-D DCT with on-line arithmetic. The utilization of on-line arithmetic, in combination with an algorithm based on FCT and matrix multiplication, reduces the total hardware maintaining a data rate and a latency similar to approaches based on distributed or parallel arithmetic. The architecture has been integrated in a chip using a 1 /spl mu/ CMOS technology, occupying an area of 56.7 mm/sup 2/.