A modified radix-24 SDF pipelined OFDM module for FPGA based MB-OFDM UWB systems

The OFDM module in the MB-OFDM UWB transmitter is necessarily operated at 528 MHz. This is really a challenging task because the OFDM in the UWB module has to calculate 128-point IFFT. Earlier papers used radix-2
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SDF algorithm with parallel processing architectures of block size two to achieve the required speed and implemented the module on ASIC. In this paper a novel scheme “modified radix-2
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SDF algorithm” is proposed to achieve the calculation of 128-point IFFT. In the proposed scheme, the order of the twiddle factor sequence is different compared to the earlier radix-2
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SDF algorithm. The change in twiddle factor sequence achieves easier implementation of the CSD multiplier used for IFFT calculation. It is also proposed that the required speed can be achieved on FPGA itself without using parallel processing architectures. This can be done by pipelining the OFDM module as well as using LPMs. This leads to reduction in area compared to the earlier approach of using parallel processing architectures of block size two. For improving the accuracy, in the proposed scheme the internal wordlength is maintained at 13bits which is 7 bits more than the input, to account for the overflows at each of the 7 stages of the OFDM module. The proposed scheme with increased complexity for better accuracy is tested on ALTERA Stratix III EP3SL50F484C2 device. From the implementation, it is verified that the OFDM module achieves a maximum clock speed of 528 MSamples/s. In general ASICs are three times faster than FPGA, operating the ASIC based OFDM module in 528 MHz with the proposed modified radix-2
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SDF pipelined algorithm is very much easier.