A Delay Generation Technique for Narrow Time Interval Measurement

A new architecture for the on-chip measurement of short-time intervals is proposed in this paper. The measurement method is similar to a typical low-voltage measurement setup where the input signals are first amplified and then measured to relax the dynamic range of the succeeding analog-to-digital converter. In the proposed method, narrow time intervals are first amplified by a time amplifier (TAMP) and then measured by a time-to-digital converter. A delay-locked-loop (DLL) circuit is utilized to design a feedback time amplifier in which the gain is readily programmed by input data to any integer value within a range specified by the number of delay cells in the DLL. The TAMP's gain remains rather unchanged under process and temperature variations due to the inherent negative feedback of the DLL system. The circuit is implemented using complementary metal--oxide semiconductor (CMOS) 0.18- mum technology occupying less than 0.63 mm
²
of the silicon area. The simulation results show that the proposed scheme can successfully be employed to measure time intervals in the range of a few tens of picoseconds with acceptable accuracy.