Performance analysis of high-speed multi-rail data transmission on SMP based architecture

We present some ideas for designing software architecture that optimizes the resource arrangement of the operating system and application programs in a PC so that Nx10 Gbps near line-rate multi-rail data transmission can be achieved using most popular SMP-based high-end PC architecture. We evaluated the effectiveness of the computation resource arrangement policies we have presented by experimentation. These are necessary because current PC architecture does not make maximum use of multi-rail data links without tactful management of processors, memories and peripheral control. Multi-rail data transmission and multi-wavelength networking devices will be the key to creating next generation terabit LANs.