Optimized Design and Implementation of Three-Phase PLL Based on FPGA

An optimized method to design and implement digital three-phase phase-locked loop (PLL) based on FPGA is presented in this paper. The PLL fits in electric power system as well as other fields. At first, principle and basic structure of the PLL including phase discriminator, loop filter and voltage controlled oscillator (VCO) are introduced, then these modules are designed in VHDL language with blocking design method. In order to save logic resource of FPGA, an optimized method called chip area sharing is adopted. At the same time, a new method which combines CORDIC algorithm with look-up table algorithm is put forward in this paper to generate sine function. This new method can both increase calculating speed and guarantee accuracy of results. At last, the design is implemented on Alterapsilas FPGA chip EP1C12Q240C8. It is verified that the design can save logic resource of FPGA largely, and it is also proved that the PLL can track the variation of frequency and lock the basic phase well.