Effect of gate bias on channel in depletion-all-around operation of the SOI four-gate transistor

In depletion-all around (DAA) operation of SOI four-gate transistor (G
⁴
-FET), the conducting channel can be surrounded by depletion regions induced by independent vertical MOS gates and lateral JFET gates. This enables majority carriers to flow through the volume of the silicon film far from both silicon/oxide and p+ gate/n-channel interfaces. A numerical model using FEMLAB with MATLAB is developed to obtain the potential distribution solving 2-D Poisson equation using finite element method. This model is extendable to fully depleted (FD) structure. Using this model, effect of gate bias on the location and size of the conducting channel is studied. Gradual change of the size of the conducting channel from drain to source is also studied when drain is positively biased. Under appropriate gate bias voltages, the cross-section of the channel may be made sufficiently narrow to invoke quantum mechanical effects.