Chip Package Interaction analysis for Cu/Ultra low-k large die Flip Chip Ball Grid Array

The impact of Chip-Package Interaction (CPI) which is caused by the mismatch in the coefficient of thermal expansion (CTE) between substrate and chip in a Flip Chip Ball Grid Array (FCBGA) on the mechanical reliability of Cu/Ultra low-k in a larger die was investigated using Finite Element Analysis (FEA). In order to associate the deformation and thermal stresses in FCBGA with those in the Cu/Ultra low-k structure which has a large difference of dimension, multi-step sub-modeling technique was used. The energy release rate (ERR) which indicates the driving force for delamination at the specific interfaces in Cu/Ultra low-k structures was calculated using modified virtual crack closure (MVCC) method to assess the mechanical reliability. The ERR at the different interfaces in four metal layers (M1 to M4) model were calculated to find the effect of mechanical properties of dielectrics on CPI. The ERR at the interface in the upper layer was higher than that at the lower layer, when ultra low-k is used in M1 and M2 layers and SiOC is used in M3 and M4 layers. However, the ERR at M4 interface becomes about 33% lower when SiO
2
is used in M4 level. This result indicates that the mechanical properties of dielectrics are important to control CPI. Then, the ERR of nine metal layers (M1 to M9) model was calculated to improve the accuracy of simulations where the dimension of interconnect structures were determined by the design rule for 90nm technology node. In this model, the ERR at M9 layer decreased significantly with W trench between A1 pad and M8 layer which indicates that the interconnect structure affects the CPI. Finally, the bump layout impacts on CPI were investigated. The highest equivalent stress near the under bump material (UBM) of the outer most solder bump was reduced about 20% by placing two extra solder bumps next to it. This result indicates that the layout of solder bump affects CPI, as well. Based on these study, the guideline to improve the mechanical reliability of Cu/Ultra low-k Interconnect in FCBGA by the material selection for interconnect and by optimizing the interconnect structure and the bump layout will be discussed.