Optimized CML circuits for 10-Gb/s backplane transmission with 120-nm CMOS technology

In this paper, we discuss an optimized current-mode logic (CML) circuit design technique for high-speed backplane transmission. The inductorless CML circuits are extensively used in high-speed digital circuits. With a given CMOS technology, the CML circuits can be optimally biased for higher speed operation with the considerations of speed, swing, power, load capacitance and area. Typical high-speed CML buffer and latch for 10-Gb/s transmission are designed with the optimized biasing technique with lower power consumption, and compact area (buffer: 10.2 times 14.4 mum
²
, latch: 30.4 times 32.8 mum
²
).