Congestion Aware High Level Synthesis Combined with Floorplanning

As VLSI gets large and complicated, routing congestion becomes more and more difficult to handle. In the traditional design flow, very little physical information is available at the high-level synthesis stage. To decrease the routing congestion and improve circuit’s performance, we propose a routing congestion aware high level synthesis method, which is based on simulated annealing (SA) algorithm. The method has two loops, the inner loop is a practical iteration, and the outer loop is a gradually cooling process. After the high level synthesis, we accept or reject the new result according to the cost function value which is obtained by fore-placement. Experimental results show that our method is more effective than traditional method and CRSF (Congestion driven re-synthesis after floorplanning ) algorithm.