ATM Cell Scheduling and Learning by Function-Level Evolvable Hardware

The possibility of using Evolvable Hardware (EHW) for scheduling real–time traffic in Asynchronous Transfer Mode (ATM) networks have studied in this paper. EHW is hardware built on programmable logic devices and whose architecture can be reconfigured by using genetic learning to adapt to new environments. A novel design is the function-level EHW based on Field programmable Gate Array (FPGA) chips. A number of Programmable Floating Processing Units (PFUs) are embedded in on chip. The selectable high-level hardware functions of each PFU make the function-level PFU make the function-level EHW to be suitable for a wide variety of applications in practice.