A programmable duty cycle corrector based on delta-sigma modulated PWM mechanism

A new programmable duty cycle corrector (PDCC) with variable duty cycle of output clock and synchronization of the input clock and output clock is proposed. Since the conventional pulse-width control circuits can adjust duty cycle but canpsilat synchronize the input and output clocks, the proposed PDCC uses a 2
^nd
-order Delta-Sigma modulator to produce more several kinds of duty-cycle selection of clock signals with a 7-bit resolution. Simulated in a 0.18 um CMOS technology, the proposed PDCC can operate from 500 MHz to 800 MHz and the duty-cycle range of input clock can be operated from 10% to 90%. Moreover, the duty cycle of the output clock can be adjusted from 25% to 75% in a fine step of 0.78%.