Multi-Vth FinFET sequential circuits with independent-gate bias and work-function engineering for reduced power consumption

Brute-force sequential circuits with reduced clock load and simpler circuitry are widely used in the state-of-the-art integrated circuits. In this paper, new multi threshold voltage (multi-V
_th
) brute-force sequential circuits based on independent-gate bias and work-function engineering are proposed for reducing the power consumption while maintaining similar speed and noise immunity characteristics as compared to the standard single threshold voltage (single-V
_th
) tied-gate FinFET circuits. With the proposed latches and flip-flops, the total active mode power consumption, the clock power, and the average leakage power are reduced by up to 55%, 29%, and 53%, respectively, while maintaining similar speed and data stability as compared to the circuits with single-V
_th
tied-gate FinFETs in a 32nm FinFET technology. Furthermore, the area is reduced by up to 21% with the new sequential circuits as compared to the circuits with single-V
_th
tied-gate FinFETs.