A two-stage pipelined passive charge-sharing SAR ADC

This paper presents a new ADC based on using passive charge sharing SAR ADC in a 2-stage pipeline architecture. The charge domain operation of passive charge sharing ADC poses an inherent limitation on its resolution. The proposed architecture increases the achievable resolution with a low power overhead. Designed and simulated in a 0.18um CMOS process, the 12-bits, 40MS/sec ADC core consumes 7mW from a 1.8V supply.