A 10MHz to 600MHz low jitter CMOS PLL for clock multiplication

This paper describes a phase-locked loop (PLL) designed for clock multiplication. The PLL has a locking range from 10MHz to 600MHz at 1.8V power supply. It has a very low peak-to-peak jitter which less than 50ps at 150MHz output frequency. It has been fabricated in a 0.18μm CMOS process. The area of the active layout of the PLL is 560μm*400μm, and power consumption is about 6mW.