A low power SHA-less pipelined ADC used in DVB-S2

A 8-b 125 MS/s pipelined analog-to-digital converter (ADC) used in DVB-S2 is presented in this paper. Based on reviewing low-power design techniques of high speed ADCs, several technologies are used in the design including the SHA-less architecture to reduce the power dissipation significantly. Detailed analysis is given about the relationship between the closed loop bandwidth (BW
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) and the current of operational amplifier (OPAMP) used in multiply digital-to-analog converter (MDAC) to get the lowest power dissipation which can satisfy the ADC. The ADC is realized in SMIC 0.18 um 1P6M CMOS process and according to the simulation results, the SNDR is 48 dB with the power of 23.5 mW.