High speed CMOS output stage for integrated DC-DC converters

A Hybrid Waffle layout technique is introduced for the design of CMOS power transistors in integrated low voltage DC-DC converters. Comparing with conventional Multi-Finger layout scheme, the Hybrid Waffle layout scheme allows optimized trade-off between device on-resistance and metal interconnect resistance to minimize overall on-resistance. Interestingly, the reduced channel width per unit area also leads to lower gate capacitance and faster switching speed. This paper presents a prototype DC-DC converter IC that contains integrated gate drivers, protection circuits and CMOS output transistors. Implemented in a standard 0.25μm CMOS, this IC can be switched at 12.5MHz with output current rated at 800mA with input voltage of up to 4.2V. Peak power efficiency of 85% was observed at 100mA. Die size is 1.1 x 1.5 mm
²
.