A novel DCPLL with small-area and low-power DCO for SoC applications

This paper presents a novel digitally controlled phase-locked loop (DCPLL) for SoC applications. The DCO of the DCPLL is designed by a flexible design method. By the method, a high performance of DCO can be implemented in a straightforward way. Finally, the DCPLL design is implemented by SMIC 0.18 ¿m logic 1P6M CMOS technology. The area of the DCPLL is 0.08 mm
²
. The post-layout simulation results by Spice show that the frequency range of the digitally controlled oscillator (DCO) is from 96 MHz to 542.5 MHz and the resolution of the DCO is about 22 ps. The power consumption of the DCPLL is 6.14 mW when the DCO operates at 400 MHz.