Aspect ratio trapping heteroepitaxy for integration of germanium and compound semiconductors on silicon

Heterogeneous integration of high quality germanium and compound semiconductors onto large-size low-cost substrates holds great promise to improve the performance and functionality of silicon-based CMOS logic beyond Moore’s Law, as well as to reduce the cost of compound semiconductor-based devices and circuits. In this article, the Aspect Ratio Trapping heteroepitaxy technique, a recently developed approach for integration of highly mismatched semiconductor materials, is presented. Its potential applications in Si-based CMOS, and in compound semiconductor-based electronics and optoelectronics device, are also discussed.