Electrostatic discharge protection framework for mixed-signal high voltage CMOS applications

Electrostatic discharge (ESD) protection requirements for high voltage (HV) MOS technology are continuously evolving and increasingly stringent. To address the ever changing technology ESD constraints, a method for design, characterization, and integration of reliable mixed-signal HV MOS ESD solutions is introduced in this study. The dynamic response, design trade-offs and ESD verification in two HV CMOS-based technologies are discussed and depicted via fast transient and quasi-static measurements in the ESD-time domain.