On-state resistance improvement by partially slotted STI LDMOS transistor in 0.25-micron smart power technology

The improvement of on-state resistance with partially slotted STI (Shallow Trench Isolation) for medium voltage power devices in an advanced 0.25um BiCMOS-DMOS process is implemented. Experiment results show that our proposed device can reduce 20% R
ON
without hurting breakdown voltage. The partially slotted STI structure avoids breakdown voltage to decrease and also shortens the drain current path due to a 3-dimentional electric field shaping. Careful design for slotted STI profile is needed to achieve the optimum R
ON
-BV tradeoff performance.